IEEE 1149.x standard contents
|1149.1||test for digital assemblies|
|1149.4||test for mixed signal and analog assemblies|
|1149.5||test at system level|
|1149.2||Obsoleted, merged with 1149.1|
|1149.3||become defunct (Obsolete)|
|1532||derivative standard for in-system programming of digital devices|
JTAG Boundary scan basicsIEEE Std 1149.1-1990 and IEEE Std 1149.1a-1993 define the architecture of the Test Access Port (TAP) and shift-registers implemented in boundary-scan devices.
For boundary scan testing, signal pins of compliant semiconductor devices are typically connected to cells in a parallel-in, parallel-out shift register. This shift-register forms a path around the periphery or the boundary of the semiconductor device. The entry and exit points of the shift register are connected to the TDI and TDO pins respectively, thus allowing access to signal pins. By sending proper "test vectors" down the boundary register, and by enabling test vectors onto the device pins, various tests can be performed.