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Q: What does "Boundary Scan" mean?
Answer:
Boundary scan is a method for testing interconnects (thin wire lines) on printed circuit boards or sub-blocks inside an integrated circuit.The boundary scan architecture provides the means to test interconnects and clusters of logic, memories etc. without using physical test probes. It adds one or more so called 'test cells' connected to each pin of the device that can then selectively override the functionality of that pin. These cells can be programmed via the JTAG scan chain to drive a signal onto a pin and across an individual trace on the board. The cell at the destination of the board trace can then be programmed to read the value at the pin, verifying the board trace properly connects the two pins. If the trace is shortened to another signal or if the trace has been cut, the correct signal value will not show up at the destination pin, and the board will be known to have a fault.
When performing boundary scan inside integrated circuits, cells are added between logical design blocks in order to be able to control them in the same manner as if they were physically independent circuits.
For normal operation, the added boundary scan latch cells are set so that they have no effect on the circuit, and are therefore effectively invisible. However, when the circuit is set into a test mode, the latches enable a data stream to be passed from one latch to the next. Once the complete data word has been passed into the circuit under test, it can be latched into place.
As the cells can be used to force data into the board, they can set up test conditions. The relevant states can then be fed back into the test system by clocking the data word back so that it can be analysed.
By adopting this technique, it is possible for a test system to gain test access to a board. As most of today’s boards are very densely populated with components and tracks, it is very difficult for test systems to access the relevant areas of the board to enable them to test the board. The Boundary scan makes this possible.
Related links
- JTAGTest IEEE 1149.1 JTAG Boundary Scan Debugger / Tester
- ViaTAP, a high-speed JTAG-USB interface
- BSDL Files
- JTAG-related standards
SECONS Ltd. is not in any way connected with integrated circuit manufacturers and there is no any type of authorization, association or affiliation between SECONS and integrated circuit manufacturers. All information present in this FAQ is provided for informational purposes only, on "as-is" basis, and is intended to be useful and informative for SECONS customers.